Class D Audio Amplifier with Trim-able Ramp Generator Design Theory and Design implementation for portable applications

This paper presents a single chip class D amplifier with two selectable gains 6dB & 9dB, 1.4 W output power and 86% efficiency with an 8 ohm load. This chip uses a frequencies trim-able ramp generator. Input Clock Frequency Range with 250kHz – 550kHz and 8 bits trim, 4 bits (LSB) to trim the ramp amplitude to vdd/5 peak-to-peak, 4 bits (MSB) to adjust the ramp continuity, the trimming procedures consists on putting a zero input signal, and adjust the trim code such as to get a 50% duty cycle Pulse Wide Modulation output signal, Reduction of inter- modulation in case of mixing of Audio and Voice. It operates with a 2.5 V to 5.5V supply voltage, 0.5 um, double-poly, triple-metal BiCMOS process. It has an area of 1.5 x 1.2 mm2 and it achieves a THD as low as 0.04%, with a flat band response between 20 Hz and 20 kHz.This paper presents a single chip class D amplifier with two selectable gains 6dB & 9dB, 1.4 W output power and 86% efficiency with an 8 ohm load. This chip uses a frequencies trim-able ramp generator. Input Clock Frequency Range with 250kHz – 550kHz and 8 bits trim, 4 bits (LSB) to trim the ramp amplitude to vdd/5 peak-to-peak, 4 bits (MSB) to adjust the ramp continuity, the trimming procedures consists on putting a zero input signal, and adjust the trim code such as to get a 50% duty cycle Pulse Wide Modulation output signal, Reduction of inter- modulation in case of mixing of Audio and Voice. It operates with a 2.5 V to 5.5V supply voltage, 0.5 um, double-poly, triple-metal BiCMOS process. It has an area of 1.5 x 1.2 mm2 and it achieves a THD as low as 0.04%, with a flat band response between 20 Hz and 20 kHz

Li-Ion battery charger for Systems RF wireless

International audienceThe design of a Li-Ion battery charger for System RF wireless is presented in this paper. The proposed chip can create a reversible three-stage linear Li-Ion battery charger and is designed with gpdk180 nm CMOS processes. The three-stage charger functions include trickle-current charging, large-current charging and constant-voltage charging. This technique can reduce the damage of Li-Ion battery. The proposed circuit can adjust the maximum charge current of 1A, the constant voltage is set to 4.2V. Input voltage of the proposed circuit is from 4.4V to 4.8V. The average efficiency of the proposed charger is about 80%. The charger can precisely provide VOUT where range is from 2.2V to 4.2V. The chip area is 0.5×1mm

A Novel Approach to Reduce the Unicast Bandwidth of an IPTV System in a High-Speed Access Network

Channel change time is a critical quality of experience (QOE) metric for IP-based video delivery systems such as Internet Protocol Television (IPTV). An interesting channel change acceleration scheme based on peer-assisted delivery was recently proposed, which consists of deploying one FCC server (Fast Channel Change Server) in the IP backbone in order to send the unicast stream to the STB (Set-Top Box) before sending the normal multicast stream after each channel change. However, deploying such a solution will cause high bandwidth usage in the network because of the huge unicast traffic sent by the FCC server to the STBs. In this paper, we propose a new solution to reduce the bandwidth occupancy of the unicast traffic, by deploying the FCC server capabilities on the user STB. This means that, after each channel change request, the STB will receive the unicast traffic from another STB instead of the central server. By using this method, the unicast traffic will not pass through the IP network; it will be a peer-to-peer communication via the Access Network only. Extensive simulation results are presented to demonstrate the robustness of our new solution

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns

A Design of a High-Performance Analog Front-End for Passive UHF RFID Tag EPC C1G2

This paper introduces a high-performance analog front end for passive UHF RFID tag compatible with the EPC Class-1 Generation 2 (EPC C1G2) standard protocol. The proposed front end of a passive tag which contains the following modules: a power generation circuit which is composed of a matching circuit and an RF-limiter circuit, an NMOS rectifier, a DC limiter, a voltage regulation, a modulation and ASK demodulation circuit, a power-on-reset circuit, a ring oscillator which generates a clock of 1.28 MHz. The originality of this work is the proposal of a voltage regulation circuit composed of two distinct LDO regulators that share the same reference voltage and are designed to generate a Vdd1 (0.5 V) for the analog supply and Vdd2 (1 V) for digital power supply, under conditions of 50 Ω antenna, 900 MHz, a sensitivity of -24 dBm and a maximum consumption of 1 µW. The operating distance of the RFID is more than 25 meters based on the regulated 4 W effective isotropic radiated power (EIRP). The chip area of the proposed analog front end is only 79 μm × 83 μm. The simulation results in 90 nm CMOS process confirm the performance of the proposed analog front-end

Lip Reading with Hahn Convolutional Neural Networks moments

International audienceLipreading or Visual speech recognition is the process of decoding speech from speakers mouth movements. It is used for people with hearing impairment , to understand patients attained with laryngeal cancer, people with vocal cord paralysis and in noisy environment. In this paper we aim to develop a visual-only speech recognition system based only on video. Our main targeted application is in the medical field for the assistance to la-ryngectomized persons. To that end, we propose Hahn Convolutional Neu-ral Network (HCNN), a novel architecture based on Hahn moments as first layer in the Convolutional neural network (CNN) architecture. We show that HCNN helps in reducing the dimensionality of video images, in gaining training time. HCNN model is trained to classify letters, digits or words given as video images. We evaluated the proposed method on three datasets, AVLetters, OuluVS2 and BBC LRW, and we show that it achieves significant results in comparison with other works in the literature

A Design of Analog Voltage-Mode Multiplier for UHF RFID in 0.18um CMOS process

In this paper a “Low Voltage, Low Power, High Speed and High Linearity-CMOS Analog Multiplier for Modem ASK is proposed”. The multiplier circuit is implemented in 180nm CMOS technology. It can be operated even at low Supply voltage VDD=0.9V. Band width of operation is about 4.10MHz, which is suitable for high frequency/high speed applications. This device modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data

Integrated energy management converter based on maximum power point tracking for photovoltaic solar system

This paper presents an integrated power control system for photovoltaic systems based on maximum power point tracking (MPPT). The architecture presented in this paper is designed to extract more power from photovoltaic panels under different partial obscuring conditions. To control the MPPT block, the integrated system used the ripple correlation control algorithm (RCC), as well as a high-efficiency synchronous direct current (DC-DC) boost power converter. Using 180 nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed MPPT was designed, simulated, and layout in virtuoso cadence. The system is attached to a two-cell in series that generates a 5.2 V average output voltage, 656.6 mA average output current, and power efficiency of 95%. The final design occupies only 1.68 mm2